The present invention relates to differential amplifiers and, more particularly, to offset adjustment in differential amplifiers.
MOS integrated circuit differential amplifiers typically include a pair of source-coupled transistors with current sources connected to the drains of the source-coupled pair. Ideally, the sizes of the devices forming the differential amplifier (including the current sources) would be perfectly matched (i.e., identical in size, performance, etc.). However, in practice, the devices are not perfectly matched, resulting in an input offset. In many applications, this offset is undesirable. Further, the offset may change over time and environmental conditions. Therefore, in some applications, the offset of an amplifier is designed to be trimmable while in the application.
Conventional techniques to reduce input offset include performing an A/D conversion of the amplifier output when the same input signal is provided to both the positive input terminal of the amplifier and the input terminal of the gain network. The digital measurement represents the offset, which is then stored. During operation, the stored xe2x80x9coffsetxe2x80x9d is then subtracted from the A/D converted output to cancel the offset. One disadvantage of this technique is that it relies on the accuracy of the A/D conversion. Another disadvantage is that to generate an offset-compensated analog output from the amplifier, a D/A converter must be used, which will add additional error to the amplifier circuit output signal. Further, the A/D/A conversion, in effect, delays the amplifier""s output signal. In a digital system, the D/A xe2x80x9cre-conversionxe2x80x9d is not necessary, but the subtraction of the offset will add delay, which is undesirable in many applications.
Another conventional solution is autozeroing in which the autozero circuit measures the offset and stores a corresponding voltage on a capacitor. The capacitor is then switched inline with the input signal to cancel the offset. However, the capacitor can be undesirably large, especially in low speed applications, to reduce capacitor voltage decay. In addition, the autozero circuit requires switching and refresh circuitry, further increasing the size and complexity of the autozero circuit.
In accordance with aspects of the present invention, a system to adjust the offset of a differential amplifier is provided for a variety of applications (e.g., a comparator, bandgap voltage reference, operational amplifier, etc.). In one aspect of the present invention, the system includes an offset detector, a reference generator, and a trim circuit, which are connected to the differential amplifier. In one embodiment, the differential amplifier has a standard MOS differential pair implementation.
In accordance with this aspect, during an offset trimming operation, the differential amplifier is placed in an open loop configuration, with both input terminals connected to receive a common reference signal from the reference generator. If the differential amplifier has an offset, the differential amplifier""s output signal will essentially rail to either the supply voltage level or the ground level. In response to the logic level of the differential amplifier""s output signal, the offset detector provides a control signal to the trim circuit to adjust the current conducted by one leg of the differential pair to reduce current mismatch in the legs of the differential pair, thereby reducing the offset.
During normal operation, the differential amplifier is isolated from the offset detector, the reference generator, and the trim circuit. By matching the differential pair currents without the use of a relatively large autozeroing capacitor, this aspect of the invention allows the system to be relatively area-efficient while avoiding analog-to-digital conversion during normal operation (unlike the conventional systems described above). Still further, this open loop system advantageously allows the trimming circuitry to be isolated from the gain network of the amplifier. In contrast, the previously described conventional solutions are performed closed loop, which tends to place the trimming circuitry in the gain network of the amplifier, which in turn can cause inaccuracy in the gain.
In a further refinement of this aspect, this process may be performed iteratively to control the trim circuit to incrementally adjust the current conducted by a leg of the differential pair during the trimming process. In this way, the offset may be reduced to within range corresponding to an increment. In one embodiment, the trim circuit includes two sets of trim transistors, one set being connected in parallel with one transistor of the differential pair, and the other set being connected in parallel with the other transistor of the differential pair. In this embodiment, each set""s transistors have binary-weighted sizes (i.e., with the sizes being 1X, 2X, 4X, 8X and so on). Depending on the polarity of the offset, transistors in one of the sets are selectively enabled to incrementally increase the current conducted by the corresponding leg of the differential pair during the trimming operation to reduce offset.
In another aspect of the present invention, the offset detector includes an analog-to-digital converter, a microcontroller and a trim register. During a trimming operation, an amplifier output terminal is connected to the analog-to-digital converter, which then detects whether the amplifier output is a logic high or a logic low level. The microcontroller then uses this information to adjust a bit in the trim register corresponding to a bit of the binary-weighted control signal provided to the trim circuit. This process is performed iteratively until all of the bits of the control signal are determined. For example, in one embodiment, in the first cycle of the trimming operation, the microcontroller is programmed to determine the polarity of the offset and, thereby, which leg of the differential pair to enable a trim transistor (or transistors) so that the current will be increased in that leg. Then, the most significant bit of the trim register is set to one, thereby enabling the most heavily weighted (i.e., the largest sized) trim transistor of the set. In the next cycle, the analog-to-digital converter detects whether the amplifier output signal reverses polarity from the first cycle. More particularly, if the polarity reverses, enabling the most significant bit of the control signal caused the polarity of the offset to reverse. In this case, the most significant bit of the trim register is set to zero and saved. If the polarity of the amplifier""s output signal does not reverse, then the most significant bit of the trim register is set to one and saved. Similarly, in the next cycle, the next most significant bit is set to one (thereby enabling the next most heavily-weighted trim transistor) and the analog-to-digital converter detects whether the amplifier output signal reverses polarity. Depending on this outcome, the corresponding bit of the trim register is set to zero or one and saved. This process is repeated until all of the bits of the control signal are tested.
In yet another aspect of the present invention, the offset detector is implemented with a successive approximation circuit instead of an analog-to-digital converter and microcontroller.